Verification and Validation Testing

VERIFICATION AND VALIDATION TESTING 5

Verificationand Validation Testing

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Verificationand Validation Processes for System Testing

Verificationand validation are terms used in software testing. These twoprocesses are misunderstood by many people, which lead to varyinginterpretation and improper usage. The process of verification is theevaluation of work-products before the actual final product in thedevelopment phase. It helps in determining whether a product has metthe requirements specified for that particular development phase(Debbabi, 2010).This is the main objective of the verification process. Theverification personnel, therefore, ask themselves if they arebuilding a product in the right way to meet their customers’demands. They use different evaluation items such as plans, designspecifications, requirement specs, test cases and codes.

Theyreview and inspect the system in a given phase to make sure all theseparameters are met. All activities in this process are intended toproduce of high-quality software. These activities include testingthe software, analysing the design and specifications, among others.It is, therefore, an extremely relatively objective process since ifdifferent products or documents are precisely expressed, then, therewill be no need of subjective judgements in verifying software.

Validationinvolves evaluation of software in the end or the course of thedevelopment process, to determine if the product has met thespecified requirements of the business. The objective is to ensurethat customers’ needs were taken into consideration, and alsospecifications were met in all stages of product development.Validation process helps in demonstrating that the product hasfulfilled its intended purpose when placed into its rightenvironment. The question that arises in validation is whether theright product has been built for the customers. The final product orsoftware is tested against the specified requirements. This processis subjective since subjective assessments are made of how theproduct meets and solves the customers’ problems. Some of theactivities involved in the validation process include modelling ofsystem’s requirements, prototyping and also user evaluation.

Forthe Early Requirements Validation, one uncovers the incorrectrequirements and also flaws in the design process early enough, bysimulation of the system behaviorin order to validate the requirements. At the same time, one canspecify properties of the system’s design that formalizes thefunctional behaviour. The creation of High-Level System Models helpsone easily to run simulations. This includes software model, theenvironmental andphysicalaspects of thesystem. A system-level model can be used in both digital and analoghardware verification.

Atthe same time, one can verify the design through the Iterative Testand Analysis. In this analysis, system design is perfected by the useof rapid iterations and also verification cycles in the iterativetest environment. It is, therefore, possible to detect errors indesign, expose any flaws in the process and generate reusable unittests automatically. Inaddition, for the embedded software test and verification, twomethods are used which are the run-time error detection and themodel-to-software verification in the source code(Dassoet al., 2007). In the run-time error detection, products foranalysing the run-time apply formal methods on automaticallygenerated or handwritten source codes, in verifying that the codes donot have any run-time errors. In the model-to-software verification,a verified model acts as a golden reference to compare its behaviourwith software which is handwritten or model-generated. Hardware-in-the-Loop(HIL), Processor-in-the-loop (PIL) and Software-in-the-loop (SIL)testing areused in the minimization of risks for the development of systems(Fisher,2007). They enable one to test his system in real time before it isdeployed in a production environment. However, theHardware-in-the-Loop (HIL) is best used when the system has not yetbeen built, testing the performance and safety, minimizing the costdowntime and when it is difficult to physically replicate failureconditions.Itis imperative to note that it is possible for a product to pass theverification process but fail in the validation. This can happen, forinstance, when a product is built according to the specifications,but these specifications fail to meet the demands or needs of theintended customers. It can, therefore, be understood that thedifference between these two processes is the role to be played bythe specifications.

References

Debbabi,M. (2010). Verificationand validation in systems engineering: Assessing UML/SysML

Designmodels.Berlin: Springer.

Dasso,A., &amp Funes, A. (2007). Verification,validation and testing in software engineering.S.l.: Gale Virtual Reference Library.

Fisher,M. S. (2007). Softwareverification and validation: An engineering and scientific approach.New York: Springer.